Sökning: "DPLL"

Hittade 4 uppsatser innehållade ordet DPLL.

  1. 1. A Digital Phase-Locked Loop for Frequency Synthesis using an Adaptive Pulse Shrinking TDC

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Viktor Lewin; [2023]
    Nyckelord :Phase-locked loop; PLL; DPLL; Frequency Synthesis; TDC; PFD; Technology and Engineering;

    Sammanfattning : This thesis investigates a new type of Phase-Locked Loop (PLL) architecture which combines a phase/frequency detector (PFD) and a digital loop filter. The quantization is done by a time-to-digital converter which continuously shrinks the pulse coming from the PFD and registers how far it propagates. LÄS MER

  3. 2. Prototyping an mcSAT-based SMTsolver in Rust

    Master-uppsats, Uppsala universitet/Institutionen för informationsteknologi

    Författare :Dennis Örnberg; [2022]
    Nyckelord :;

    Sammanfattning : Satisfiability modulo theories, or SMT, is the decision problem of determining whether a set of formulas is satisfiable or not, given one or more background theories. The model-constructing satisfiability calculus, or mcSAT, is a framework used for solving SMT problems. LÄS MER

  4. 3. On the Structure of Resolution Refutations Generated by Modern CDCL Solvers

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Johan Lindblad; [2019]
    Nyckelord :;

    Sammanfattning : Modern solvers for the Boolean satisfiability problem (SAT) that are based on conflict-driven clause learning (CDCL) are known to be able to solve some instances significantly more efficiently than older kinds of solvers such as ones using the Davis-Putnam-Logemann-Loveland (DPLL) algorithm. In addition to solving instances that can be satisfied, SAT solvers will implicitly generate proofs of unsatisfiability for formulae that are unsatisfiable. LÄS MER

  5. 4. Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band

    Master-uppsats, Linköpings universitet/Elektroniksystem; Linköpings universitet/Tekniska högskolan

    Författare :Naveen Wali; Balamurali Radhakrishnan; [2013]
    Nyckelord :ADPLL; TDC; DPLL; PLL;

    Sammanfattning : An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. LÄS MER