Sökning: "SystemC"
Visar resultat 1 - 5 av 25 uppsatser innehållade ordet SystemC.
1. Digital Twin for Firmware and Artificial Intelligence prototyping
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : The forth industrial revolution has risen the born of new mega trends for the improvement of the time to market and the spare of resources in the development and manufacturing of a new product. Among these trends, the Digital Twin (DT) is the one of major interests for developers and strategy analysts. LÄS MER
2. Design space exploration using HLS in relation to code structuring
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : High Level Synthesis (HLS) is a methodology to translate a model developed in a high abstraction layer, e.g. C/C++/SystemC, that describes the algorithm into a Register-Transfer level (RTL) description like Verilog or VHDL. LÄS MER
3. Evaluating Temporal Decoupling in a Virtual Platform
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : To capture the market in the field of SoC, the companies have to launch their product ahead of their competitors. Virtual platforms allow the building and testing of software before the hardware is available, so the hardware and software development can take place in parallel and reduce the time to market. LÄS MER
4. MATLAB/Simulink implementation of ForSyDe
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : Nowadays, it is possible to integrate an increasing number of functionalities on a single chip thanks to the state of the art technology in Electronic design automation. However, designing highly complex electronic systems quickly and reliably requires dealing with all such functionalities, which can be difficult as it requires a long and challenging design process because low-level details are necessary to obtain a functional implementation. LÄS MER
5. Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. LÄS MER