Sökning: "se rtl"

Visar resultat 1 - 5 av 69 uppsatser innehållade orden se rtl.

1. 1. FPGA programming with VHDL : A laboratory for the students in the Switching Theory and Digital Design course

   Kandidat-uppsats, Högskolan i Halmstad

   Författare :Samaneh Azimi; Safia Abba Ali; [2023]
   Nyckelord :FPGA Field-Programmable Gate Arrays VHDL Very High-Speed Integrated Circuits HDL Hardware description language LUT Look-up-table CLB Configurable Logic Blocks MUX Multiplexers IOB Input Output Blocks DUT Device under the test ASIC Application-specific integrated circuits SOC System on chips RTL Register Transfer Language;

   Sammanfattning : This thesis aims to create effective and comprehensive learning materials for students enrolled in the Switching Theory and Digital Design course. The lab is designed to enable students to program an FPGA using VHDL in the Quartus programming environment to control traffic intersections with sensors and traffic signals. LÄS MER

3. 2. Novel Method of ASIC interface IP development using HLS

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Anestis Athanasiadis; Chandranshu Mishra; [2023]
   Nyckelord :High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

   Sammanfattning : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. LÄS MER

4. 3. Modeling, Simulation, and Injection of Camera Images/Video to Automotive Embedded ECU : Image Injection Solution for Hardware-in-the-Loop Testing

   Uppsats för yrkesexamina på avancerad nivå, Uppsala universitet/Signaler och system

   Författare :Anton Lind; [2023]
   Nyckelord :ADAS; AD; ADS; HIL; Hardware in the loop; Hardware-in-the-loop; ECU; VCU; Automotive; Embedded; System; Systems; Camera; Image; Video; Injection; FPGA; MPSoC; Vivado; Vitis; VHDL; Volvo; Cars; FMC; HPC; LPC; MIPI CSI2; GMSL2; AMBA AXI4; Xilinx; RTL; Implementation; Synthesis; Intelectual Property; IP; Vehicle computing unit; Electronic control unit; TEB0911; TEF0007; TEF0010; CSI2 Tx; CSI2 Tx Subsystem; Zynq; SerDes; AXI4; AXI4-Lite; Programmable Logic; PL; Processor System; PS; C; C ; Video test pattern generator; VTPG; Axi traffic generator; ATG; Ultrascale ; Virtual input output; VIO; Integrated logic analyzer; ILA; Interface Unit;

   Sammanfattning : Testing, verification and validation of sensors, components and systems is vital in the early-stage development of new cars with computer-in-the-car architecture. This can be done with the help of the existing technique, hardware-in-the-loop (HIL) testing which, in the close loop testing case, consists of four main parts: Real-Time Simulation Platform, Sensor Simulation PC, Interface Unit (IU), and unit under test which is, for instance, a Vehicle Computing Unit (VCU). LÄS MER

5. 4. Low-power Acceleration of Convolutional Neural Networks using Near Memory Computing on a RISC-V SoC

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Kristoffer Westring; Linus Svensson; [2023]
   Nyckelord :FPGA; ASIC; Near Memory Computing; RISC-V; Convolutional Neural Network; Technology and Engineering;

   Sammanfattning : The recent peak in interest for artificial intelligence, partly fueled by language models such as ChatGPT, is pushing the demand for machine learning and data processing in everyday applications, such as self-driving cars, where low latency is crucial and typically achieved through edge computing. The vast amount of data processing required intensifies the existing performance bottleneck of the data movement. LÄS MER

7. 5. Exploring Ethernet Switching Architectures for Area-Efficient Low-End Switches

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Jon Swedberg; Felix Ghosh; [2023]
   Nyckelord :Ethernet Switch; Architecture; Silicon Area; Area Optimization; ASIC; FPGA; Technology and Engineering;

   Sammanfattning : The aim of this thesis project has been to develop an architecture for L2 ethernet switches that would be optimized for silicon area, targeting smaller low-end switches. A selection was made of three different switching architectures, which were compared and analyzed to explore the benefits and drawbacks of different approaches. LÄS MER