Capacitance Optimization and Ballistic Modeling of Nanowire Transistors

Sammanfattning: Downscaling of Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) has contributed to increased microchip device density and to improve the functionality of the electronic circuits. The dimensions of state of art MOSFET is down to a few nanometers. It has been demonstrated that smaller MOSFETs are faster and more energy-efficient. However, with continued device scaling the performance of ICs starts to deteriorate making it important to implement new technology solutions. Nanowire transistors have in recent years been introduce to face some of semiconductor challenges, such as short-channel effects and performance degradation. The geometry of the nanowires allows the gate contact to be wrapped all-around the nanowire which offers an excellent electrostatic integrity. However, the performance of nanowire MOSFETs is restricted due to parasitic capacitances and resistances between the metal contacts and semiconductor nanowires. The presence of parasitic capacitances and resistances in devices introduces time delay, which is the time required for charging and discharging the capacitances. Insulating interlayers with high relative permittivity contribute to higher capacitances, and thereby increased time delay. There are amount of materials with low relative permittivity that are suitable to replace the conventionally used spacer material, SiO2. The high k-value of SiO2 is believed to contribute to higher parasitic capacitances, and performance degradation. Integration of Hydrogen silsesquioxane (HSQ) as an interlayer dielectric in multilevel interconnects has received much attention in semiconductor fabrication. To investigate the possibility of using HSQ as insulating material in nanowire transistors, the properties and the relative permittivity of this material should be explored. Measurement of HSQ k-value has not been done before and this value has only been speculated. Therefore, a parallelplate capacitor structure with a varying HSQ-thickness, obtained by using Electron Beam Lithography (EBL), has been manufactured to study the properties of HSQ. Furthermore, the thickness of HSQ has been estimated and CV - characteristics has been considered to measure the k-value of this material. Experimental measurements on the manufacturedstructure showed that HSQ is durable as a spacer material, and it has the capability to be used as interlayer dielectric in nanowire transistors. Additionally, the calculated relative permittivity, k, of HSQ was approximately 3.00 0.40. Furthermore, this thesis is about investigating the performance of ballistic 1-D MOSFETs at high frequencies, explaining the operational principles of these devices, calculating RF figures of merit, and extracting high frequency transistor metrics, fT and fmax. The simulation in this thesis is based on parameter optimization to find the optimal parameters that give minimized parasitic capacitances and thereby improved transistor performance. To achieve these purposes, 3D-structures have been modeled using COMSOL Multiphysics. The numerical calculations on the modeled 3D nanowire transistor structures demonstratea transition frequency fT = 480 GHz and maximum frequency fmax = 1.60 THz.