Redesign of readout driver using FPGA

Sammanfattning: In the ATLAS experiment now being finished at CERN in Geneva, bunches ofprotons will collide at a rate of 40 million times per second. Over 40 TB of datawill be generated every second. In order to reduce the amount of data to a moremanageable level, a system of triggers is put in place. The trigger system mustquickly evaluate if the data from a collision indicates that an interesting physicalprocess took place, in which case the data are to be stored for further analysis.    ATLAS uses a trigger system with three steps. The first step, the First LevelTrigger, is responsible of reducing the rate from 40MHz to 75KHz, and is donecompletely in hardware. It receives a new event every 25 ns, and must decidewithin 2.5 μs whether the event should be passed on to the next trigger level.    In this document is the redesign of two subsystems of the First Level Triggerdescribed. When prototypes were made 5-10 years ago, both subsystems used 7PLDs. Today, the same logic could be fitted in one FPGA, and because of theflexibility gained by having all logic in a single FPGA, both subsystems could berealized with the same PCB design.