Design of Pacman with Debug Logic

Sammanfattning: This thesis work was performed at Ineda System Pvt Ltd, Hyderabad, India. Pacman is an interrupt controller, designed with the concept of priority based selection of peripherals with 16x8 input interrupt lines. The main objective of this Master Thesis is to upgrade 16x8 interrupt controller and priority resolver to 128x8 input interrupt lines and adding a debug feature for this customised processor which has its own instruction set. In this thesis, the upgradation of Pacman and design of debugging features such as halt, break point, single step are implemented at the Register Transfer Level (RTL) in the processor. The processor is integrated with Memory, JtagtoAHB, System Register modules and the Advanced High-performance Bus (AHB) Arbiter. The functional correctness of the design is verified using system verilog test bench and validated the design in FPGA environment.