Sökning: "Delay locked loop"

Visar resultat 1 - 5 av 8 uppsatser innehållade orden Delay locked loop.

  1. 1. Investigation of Analog Calibration Systems for Spurious Tone Suppression in Frequency Triplers

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Cristian Alexandru Ghihanis; Barath Copparam Santhanakrishnan Sudarsan; [2023]
    Nyckelord :Delay-Locked Loop; DLL; Edge-Combining; EC; EC DLL; Edge-Combining Delay-Locked Loop; spurious tone calibration; spurs calibration; spurious tones compensation; spurs compensation; Technology and Engineering;

    Sammanfattning : The market for Wi-Fi receiver designs for latest Wi-Fi standards, that cover RF bands in the 2.4 GHz, 5 GHz and 6 GHz spectrum, require increasingly stringent power consumption limitations as more of the market is driven towards battery-powered devices. LÄS MER

  3. 2. Ultra-stable frequency transfer using optical fibers

    Master-uppsats, Lunds universitet/Atomfysik; Lunds universitet/Fysiska institutionen

    Författare :Simon Preutz; [2016]
    Nyckelord :Optics; optical fibers; stability; time; optical clocks; control.; Technology and Engineering;

    Sammanfattning : A new era of precise time measurement came with the atomic clock. The technology is vital to navigations systems like GPS and to accurate physical measurements. LÄS MER

  4. 3. Firmware Design and Implementation for a 14-bit Analog-to-Digital Converter to be used in the PANDA Experiment

    Master-uppsats, Uppsala universitet/Institutionen för informationsteknologi

    Författare :Peter Moris; [2015]
    Nyckelord :;

    Sammanfattning : Development of the VHDL firmware for a high-speed Analogue to Digital Converter (ADC) is the focus of this paper, including writing, debug- ging and evaluation of said firmware. The finished version of the firmware is able to correctly convert analogue signals received by the ADC into their digital representations. LÄS MER

  5. 4. DLL Based Reference Multiplier for the use in a PLL for WLAN applications

    Master-uppsats, Lunds universitet/Fysiska institutionen

    Författare :Kamal Gupta; [2015]
    Nyckelord :reference multiplier; Frequency synthesizer; Frequency multiplier; PLL; DLL; Delay locked loop; VCDL; inverter-based VCDL; charge pump; XOR phase detector; phase noise; 4X multiplier; Technology and Engineering;

    Sammanfattning : This master’s thesis project report deals with the design of multiplier for the reference signal to the Phase Locked Loop (PLL) used in WLAN application. The reference multiplier designed is based on a newly proposed architecture of dual loop feedback Delay Locked Loop (DLL) in which multiplication is performed within the loops. LÄS MER

  7. 5. Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band

    Master-uppsats, Linköpings universitet/Elektroniksystem; Linköpings universitet/Tekniska högskolan

    Författare :Naveen Wali; Balamurali Radhakrishnan; [2013]
    Nyckelord :ADPLL; TDC; DPLL; PLL;

    Sammanfattning : An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. LÄS MER