Sökning: "FPGA-based Simulation"

Visar resultat 1 - 5 av 13 uppsatser innehållade orden FPGA-based Simulation.

1. 1. Modeling, Simulation, and Injection of Camera Images/Video to Automotive Embedded ECU : Image Injection Solution for Hardware-in-the-Loop Testing

   Uppsats för yrkesexamina på avancerad nivå, Uppsala universitet/Signaler och system

   Författare :Anton Lind; [2023]
   Nyckelord :ADAS; AD; ADS; HIL; Hardware in the loop; Hardware-in-the-loop; ECU; VCU; Automotive; Embedded; System; Systems; Camera; Image; Video; Injection; FPGA; MPSoC; Vivado; Vitis; VHDL; Volvo; Cars; FMC; HPC; LPC; MIPI CSI2; GMSL2; AMBA AXI4; Xilinx; RTL; Implementation; Synthesis; Intelectual Property; IP; Vehicle computing unit; Electronic control unit; TEB0911; TEF0007; TEF0010; CSI2 Tx; CSI2 Tx Subsystem; Zynq; SerDes; AXI4; AXI4-Lite; Programmable Logic; PL; Processor System; PS; C; C ; Video test pattern generator; VTPG; Axi traffic generator; ATG; Ultrascale ; Virtual input output; VIO; Integrated logic analyzer; ILA; Interface Unit;

   Sammanfattning : Testing, verification and validation of sensors, components and systems is vital in the early-stage development of new cars with computer-in-the-car architecture. This can be done with the help of the existing technique, hardware-in-the-loop (HIL) testing which, in the close loop testing case, consists of four main parts: Real-Time Simulation Platform, Sensor Simulation PC, Interface Unit (IU), and unit under test which is, for instance, a Vehicle Computing Unit (VCU). LÄS MER

3. 2. Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Weijiang Kong; [2019]
   Nyckelord :LDPC; CGRA; Reconfigurable architecture; VLSI design; ASIC; LDPC; CGRA; Konfigurerbar arkitektur; VLSI design; ASIC;

   Sammanfattning : Low density parity check (LDPC) code is an error correction code that has been widely adopted as an optional error correcting operation in most of today’s communication protocols. Current design of ASIC or FPGA based LDPC accelerators can reach Gbit/s data rate. LÄS MER

4. 3. An FPGA Based MPPT and Monitoring System : suitable for a photovoltaic based microgrid

   Kandidat-uppsats, Linnéuniversitetet/Institutionen för fysik och elektroteknik (IFE)

   Författare :Rongpeng Zheng; [2019]
   Nyckelord :Microgrids; Monitoring System; Maximum Power Point Tracking MPPT ; Stand-alone Mode; Grid-connected Mode; FPGA; Verilog HDL.;

   Sammanfattning : Microgrids containing photovoltaic (PV) cells and wind power gain more and more interest. These microgrids may work in stand-alone mode ("islanding") or be conncted to the main grid. In both modes of operation, power quality must be monitored and controlled. This report focuses on microgrids and aims to implement a monitoring system based on FPGA. LÄS MER

5. 4. Accelerated Simulation of Modelica Models Using an FPGA-Based Approach

   Master-uppsats, Linköpings universitet/Datorteknik

   Författare :Herman Lundkvist; Alexander Yngve; [2018]
   Nyckelord :FPGA; Modelica; VHDL; MBSE; model simulation; ODE; HLS; hardware acceleration; PCIe; ZYNQ;

   Sammanfattning : This thesis presents Monza, a system for accelerating the simulation of modelsof physical systems described by ordinary differential equations, using a generalpurpose computer with a PCIe FPGA expansion card. The system allows bothautomatic generation of an FPGA implementation from a model described in theModelica programming language, and simulation of said system. LÄS MER

7. 5. FPGA-BASED HYBRID COMPUTING FOR ESS LINAC SIMULATOR.

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Arun Jeevaraj; [2017]
   Nyckelord :Hybrid Computing; OpenCL; FPGA; Linear Accelerator; Heterogeneous computing; Technology and Engineering;

   Sammanfattning : The thesis explores efficient implementation strategies for the European Spallation Source (ESS) linear accelerator simulator. The target simulator needs to run at real time, requires high computation accuracy, and should be scalable for high density beam scenarios. LÄS MER