Sökning: "HDL Coder"

Hittade 4 uppsatser innehållade orden HDL Coder.

1. 1. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Tor Hammarbäck; Jorge Deza Concori; [2022]
   Nyckelord :Technology and Engineering;

   Sammanfattning : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. LÄS MER

3. 2. Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments

   Uppsats för yrkesexamina på avancerad nivå, Luleå tekniska universitet/Institutionen för system- och rymdteknik

   Författare :Carl Bäck; [2020]
   Nyckelord :HLS; System Generator for DSP; Histogram; Xilinx Zynq UltraScale ; FPGA design workflow; Hardware Description Language Coder; HDL Coder; Field Programmable Gate Arrays; Image processing;

   Sammanfattning : FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. LÄS MER

4. 3. Performance Evaluation of MathWorks HDL Coder as a Vendor Independent DFE Generation

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Elisabeth Pongratz; Roshan Cherian John; [2019]
   Nyckelord :MATLAB; Simulink; HDL Coder; XSG; DSPB; Technology and Engineering;

   Sammanfattning : This thesis aims to evaluate MathWorks HDL (Hardware Descriptive Language) Coder and compare the results with designs produced by its vendor dependent counterparts. The focus is mainly on evaluate the design effort needed to close timing and to get optimal resource mapping for a selected design. LÄS MER

5. 4. High Level Synthesis of FPGA-Based Digital Filters

   Master-uppsats, Uppsala universitet/Institutionen för informationsteknologi

   Författare :Gerald Baguma; [2014]
   Nyckelord :;

   Sammanfattning : This thesis work is aimed at the high level synthesis of FPGA based IIR digital filters using Vivado HLS produced by Xilinx and HDL coder produced by MathWorks. The Higher Layer Model of the filter was designed in Vivado HLS, MATLAB and Simulink. Simulations, verification and Synthesis of the RTL code was done for both tools. LÄS MER