Sökning: "NoC router design"

Visar resultat 1 - 5 av 9 uppsatser innehållade orden NoC router design.

1. 1. Virtual-Channel Based Wormhole NoC on FPGA for ForSyDe/NoC System Generator Tool Suite

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Zhang Runzi; [2018]
   Nyckelord :;

   Sammanfattning : Nowadays, the number of processors integrated on system-on-chip (SoC) increases rapidly and makes multiprocessor system-on-chip design (MPSoC) a regular feature of the embedded system. [25] To support the communication between several homogeneous or heterogeneous processors a communication infrastructure, Networkon-Chip (NoC) technology was raised more than ten years ago. LÄS MER

3. 2. A Reconfigurable Device for GALS Systems

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Rocco Sciaraffa; [2018]
   Nyckelord :FPGA; GALS; asynchronous; coarse-grained; NoC; bundled-data; FPGA; GALS; asynkron; Coarse-Grained Reconfigu- rable; NoC; bundled data kommunikation;

   Sammanfattning : Globally Asynchronous Locally Synchronous (GALS) Field-Programmable Gate Array (FPGA) are composed of standard synchronous reconfigurable logic islands that communicate with each other via an asynchronous means. Past research into fully asynchronous FPGA has demonstrated high throughput and reliability adopting dual-rail encoding. LÄS MER

4. 3. Short Message Network-On-Chip Interconnect for ASIC

   Master-uppsats, KTH/Skolan för informations- och kommunikationsteknik (ICT)

   Författare :Ejaz Sadiq; [2014]
   Nyckelord :;

   Sammanfattning : The rise of large scale integration has resulted in large number of processing elements/cores on a single ASIC. Thus an efficient interconnect scheme between the different processing elements and interfaces is required. Bus based interconnect poses problems such as non-scalability. LÄS MER

5. 4. Router Architecture for Junction Based Source Routing:Design and FPGA Prototyping

   Master-uppsats, JTH, Data- och elektroteknik

   Författare :Muhammad Awais Aslam; [2012]
   Nyckelord :JBR router; router architecture; NoC router design; router architecture for JBR;

   Sammanfattning : The increase in the number of cores that can be integrated on a single chip has forced the designer to use computer network concepts for design of System on Chip (SoC). This idea led to development of Network on Chip (NoC) to deal with more cores on a single chip. LÄS MER

7. 5. DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP

   Master-uppsats, JTH, Data- och elektroteknik

   Författare :Adnan Mahmood; Zaheer Ahmed Mohammed; [2009]
   Nyckelord :Network on Chip NoC ; System on Chip SoC ; Resource Network Interface RNI ; Altera FPGA; Nios II Core; On Chip Communication; Distributed Routing; Source Routing;

   Sammanfattning : Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). LÄS MER