Sökning: "PLL."

Visar resultat 1 - 5 av 51 uppsatser innehållade ordet PLL..

1. 1. Development and Analysis of Small Signal DQ-Frame Model for Low Frequency Stability of Train Converters

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Fabian Tidner; [2023]
   Nyckelord :Low Frequency stability; DQ-frame modeling; Single phase converter; Electric rail way systems; Lågfrekvent stabilitet; DQ-ram modellering; Enfasig likriktare; Elektriska järnvägssystem;

   Sammanfattning : In order to meet the increasing demand for sustainable transportation, trains need to run with tighter schedules, more departures and more trains in depot. Multiple trains in depot has been linked to low frequency instability at many locations around the world. LÄS MER

3. 2. A Low Noise Digitally Controlled Oscillator for a Wi-Fi 6 All-Digital PLL

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Tommy Lundberg; [2023]
   Nyckelord :Digitally Controlled Oscillator; All-Digital Phase Locked Loop; Oscillator; Low Phase Noise; Class-C oscillator; Dual-Core; Dynamic BiasingCircuit; Digitalt Styrd Oscillator; Digital PLL; Lågt Fasbrus; Klass-C Oscillator; Dubbelkärnig; Dynamisk Bias-Krets;

   Sammanfattning : Following the rise of Internet of Things (IoT), or just the technological advancements and expectations in a world where the things are or will be connected, new demands are put on Integrated Circuit (IC) for wireless connectivity. The use cases seem endless; smart home, healthcare, entertainment, and science are all areas that can benefit from connectivity of low power electronics. LÄS MER

4. 3. Phase Noise Performance of a PLL Frequency Synthesizer when Powered by Silent Switchers

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Sampriti Basu; [2023]
   Nyckelord :Silent Switcher; PLL synthesizer; Phase noise; PCB implementation.; Silent Switcher; PLL-synthesizer; fasbrus; PCB-implementering.;

   Sammanfattning : In use today are ‘normal’ DC-DC switching regulators with considerable switching noise and ringing, which is bad for noise-sensitive applications. This project involves a solution based on ‘Silent Switchers’ to prove its effectiveness in reducing noise. LÄS MER

5. 4. A Digital Phase-Locked Loop for Frequency Synthesis using an Adaptive Pulse Shrinking TDC

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Viktor Lewin; [2023]
   Nyckelord :Phase-locked loop; PLL; DPLL; Frequency Synthesis; TDC; PFD; Technology and Engineering;

   Sammanfattning : This thesis investigates a new type of Phase-Locked Loop (PLL) architecture which combines a phase/frequency detector (PFD) and a digital loop filter. The quantization is done by a time-to-digital converter which continuously shrinks the pulse coming from the PFD and registers how far it propagates. LÄS MER

7. 5. A digital integer-N PLL architecture using a pulse-shrinking TDC for mmWave applications.

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Simon Richter; [2023]
   Nyckelord :Phase-locked-loops; All-digital Phase-locked-loops; Time-to-digital converters; 5G and beyond; Radio-frequency design; Fas-låsd-loop; Helt-digital fas-låst-loop; Tid-till-digital-omvandlare; 5G och framtiden; Radio-frekvens design;

   Sammanfattning : With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. LÄS MER