Sökning: "Pipelined"

Visar resultat 1 - 5 av 38 uppsatser innehållade ordet Pipelined.

  1. 1. Simulated molecular adder circuits on a surface of DNA : Studying the scalability of surface chemical reaction network digital logic circuits

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Jakob Arvidsson; [2023]
    Nyckelord :Surface chemical reaction networks; Molecular computing; DNA computing; Circuit simulation; Adders; Ytbundna kemiska reaktionsnätverk; Molekylär beräkning; DNA-beräkning; Kretssimulering; Additionskretsar;

    Sammanfattning : The behavior of the Deoxyribonucleic Acid (DNA) molecule can be exploited to perform useful computation. It can also be ”programmed” using the language of Chemical Reaction Networks (CRNs). One specialized CRN construct is the Surface Chemical Reaction Network (SCRN). LÄS MER

  3. 2. Latency Bounds for Memory-Based FFTs with Applications in OFDM Communication

    Master-uppsats, Linköpings universitet/Institutionen för systemteknik

    Författare :Xiangbin Tan; Tadesse Hadush Negash; [2023]
    Nyckelord :FFT; scheduling; memory-based architecture; latency;

    Sammanfattning : Future communication systems require low latency Fast Fourier transform (FFT)computation with a small cost of area. In this study, a memory-based FFT processorwith low latency is designed. LÄS MER

  4. 3. Data Collection and Layout Analysis on Visually Rich Documents using Multi-Modular Deep Learning.

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Mattias Stahre; [2022]
    Nyckelord :DeepLearning; Machine Learning; Dataset Collection; Annotation; Labeling; Transformer Network; Multi-Modal; Computer Vision; Natural Language Processing; Embedding; LayoutLMv2; DocBank; Djupinlärning; Maskininlärning; Datasamling; Annotering; Märkning; Transformernätverk; Multi-modulär; Datorsyn; Naturlig Språkbehandling; Inbäddning; LayoutLMv2; DocBank;

    Sammanfattning : The use of Deep Learning methods for Document Understanding has been embraced by the research community in recent years. A requirement for Deep Learning methods and especially Transformer Networks, is access to large datasets. LÄS MER

  5. 4. Design a Three-Stage Pipelined RISC-V Processor Using SystemVerilog

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Ziyan He; [2022]
    Nyckelord :RISC; RISC-V; ISA; SystemVerilog; RTL simulation; RV32IM; CPI; RISC; RISC-V; ISA; SystemVerilog; RTL simulering; RV32IM; CPI;

    Sammanfattning : RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. LÄS MER

  7. 5. A design of a 100 MS/s, 8-bit Pipelined ADC in CMOS

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Shen Zhang; [2021]
    Nyckelord :Technology and Engineering;

    Sammanfattning : The thesis focuses on designing and simulating an 8-bit high-speed fully differential pipelined Analog to Digital Converter (ADC) in the 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology by using the software Cadence Virtuoso. The aim is to increase the operation speed of the ADC for communication systems without reducing the performance, in the meantime, the low power consumption and the low complexity should also be required when considering future implementation. LÄS MER