Sökning: "SOC Verification"

Visar resultat 1 - 5 av 15 uppsatser innehållade orden SOC Verification.

  1. 1. Investigating Machine Learning for verification of AMBA APB protocol.

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Abhiram Srisai Kishore; Mohammed Wasim; [2022]
    Nyckelord :Machine learning; SOC Verification; AMBA; Neural Networks; Deep Learning; Assertions.; Technology and Engineering;

    Sammanfattning : It is a well-known fact that in any Application Specific Integrated Circuit (ASIC) design, verification consumes most time and resources. And when it comes to huge designs, finding bugs can be tedious given the area and the complexity. As per Moore’s law, the design complexity is increasing exponentially due to the growing demand for performance. LÄS MER

  2. 2. Utveckling av en kompakt BLE-modul i en portabel EKG : Med möjlighet till kontinuerlig dataöverföring

    M1-uppsats, Linköpings universitet/Elektroniska Kretsar och System

    Författare :Henrik Attrell; Mattias Holmqvist; [2022]
    Nyckelord :ECG; Electronics; ADS1298; BLE; Bluetooth Low Energy; elektronik; EKG; portabel; ADS1298; BLE; Bluetooth Low Energy; nRF52;

    Sammanfattning : Elektrodiagram eller EKG används inom sjukvården för att mäta hjärtats elektriska aktivitet med hjälp av flera elektroder som placeras ut på kroppen. Från mätningarna kan indikationer på hjärtsjukdomar och störningar i hjärtrytm upptäckas och sedan behandlas. LÄS MER

  3. 3. Energy efficient Ericsson Many-Core Architecture (EMCA) IP blocks for 5G ASIC

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Zilin Zhang; [2021]
    Nyckelord :Technology and Engineering;

    Sammanfattning : Power consumption has become a leading concern for SoC aimed at 5G products that demand increased functionality, smaller form factors, and low energy footprint. For some EMCA IP blocks a hierarchical clock gating mechanism ensures coarse-grained power savings based on actual processing need but for many blocks this approach cannot be employed. LÄS MER

  4. 4. Low power memory controller subsystem IP exploration using RTL power flow : An End-to-end power analysis and reduction Methodology

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Neerajnayan Balachandran; [2020]
    Nyckelord :Power analysis; Block characterization; Optimization; Differential Energy analysis; Dynamic Power; Clock gating.; Power-analys; Block karakterisering; Optimering; Differential Energy-analys; Dynamic Power; Clock gating;

    Sammanfattning : With FinFET based Application Specific Integrated Circuit (ASIC) designs delivering on the promises of scalability, performance, and power, the road ahead is bumpy with technical challenges in building efficient ASICs. Designers can no longer rely on the ‘auto-scaling’ power reduction that follows technology node scaling, in these times when 7nm presents itself as a ‘long-lived’ node. LÄS MER

  5. 5. Spice Circuit Reduction for Speeding up Simulation and Verification

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Menglin Wang; Cancan Yin; [2019]
    Nyckelord :Technology and Engineering;

    Sammanfattning : The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit. LÄS MER