Sökning: "SOC Verification"
Visar resultat 6 - 10 av 16 uppsatser innehållade orden SOC Verification.
6. Spice Circuit Reduction for Speeding up Simulation and Verification
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit. LÄS MER
7. A Technology Agnostic Approach for Standard-cell Layout Design Automation
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly contains millions of standard cells. The sheer amount implies that even small optimizations on a standard cell can have a significant effect on the SoC performance. To ensure the performance of standard cells, many of these are hand-drawn. LÄS MER
8. Evaluating Parallelization Potential for a SystemC/TLM-based Virtual Platform
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : System on chip (SoC) solutions, with integrated hardware and embedded software, are increasing in size and complexity. To cope with the market demand for complex SoC, the abstraction level used during development is raised to allow co-development of software (SW) and hardware (HW). LÄS MER
9. Wireless System on Virtual Platform Evaluation
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : The most common way to develop System-on-Chip's (SoC) today is to utilize hardware design on a Field programmable gate array (FPGA). By utilizing the hardware on an FPGA, the opportunity to verify the hardware and start software design before implementing the final solution on silicon is possible. LÄS MER
10. Virtual Cycle-accurate Hardware and Software Co-simulation Platform for Cellular IoT
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : Modern embedded development flows often depend on FPGA board usage for pre-ASIC system verification. The purpose of this project is to instead explore the usage of Electronic System Level (ESL) hardware-software co-simulation through the usage of ARM SoC Designer tool to create a virtual prototype of a cellular IoT modem and thereafter compare the benefits of including such a methodology into the early development cycle. LÄS MER