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  1. 1. Time to Digital Converter used in ALL digital PLL

    Master-uppsats, KTH/Skolan för informations- och kommunikationsteknik (ICT)

    Författare :Chen Yao; [2011]
    Nyckelord :All Digital PLL; Time to Digital Converter TDC ; Sensed Amplifier Flip Flop SAFF ; Current Starved; Vernier delay line;

    Sammanfattning : This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. LÄS MER