Sökning: "System Verilog"

Visar resultat 1 - 5 av 26 uppsatser innehållade orden System Verilog.

1. 1. Novel Method of ASIC interface IP development using HLS

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Anestis Athanasiadis; Chandranshu Mishra; [2023]
   Nyckelord :High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

   Sammanfattning : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. LÄS MER

3. 2. Exploiting Spatial Redundancy and Approximate Computing for Area Efficient Image Compression

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Saurav Arjun; [2022]
   Nyckelord :Image Compression; VLSI; Spatial redundancy; DCT; Compression; System Verilog; Technology and Engineering;

   Sammanfattning : Owing to the intensive computation involved in the Discrete Cosine Transform during image com- pression, the design of the efficient hardware architectures for fast computation of the transform has become imperative, especially for real-time applications. Although fast computation techniques have been able to minimise the hardware computation complexity to a certain limit, they could further extend the research to figure out the interesting approaches which can be implemented on applications where power, speed and area are crucial factors to determine the performance of the system. LÄS MER

4. 3. D-band Power Amplifiers in Vertical InGaAs Nanowire MOSFET Technology for 100 Gbps Wireless Communication

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Patrik Blomberg; Ludvig Pile; [2022]
   Nyckelord :D-band; Power Amplifier; Pseudo-differential common source; Stacked; Vertical InGaAs nanowire; MOSFET; Technology and Engineering;

   Sammanfattning : Two different topologies of power amplifiers (PAs) are designed in the frequency range 130-174.8 GHz for use in backhaul transmitters. These are the pseudo-differential common source (PDCS) and the single-ended stacked amplifier topologies. LÄS MER

5. 4. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Tor Hammarbäck; Jorge Deza Concori; [2022]
   Nyckelord :Technology and Engineering;

   Sammanfattning : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. LÄS MER

7. 5. Validation of efficiency of formal verification methodology for verification closure

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Gautham Prabhakar; [2022]
   Nyckelord :UVM; formal verification; assertions; verification engineers; SVA; TLV; jasper gold; UVM; formell verifiering; assertions; verifierar; SVA; TLV; jasper gold;

   Sammanfattning : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. LÄS MER