Sökning: "folded cascode"

Hittade 5 uppsatser innehållade orden folded cascode.

  1. 1. Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS

    Master-uppsats, Linköpings universitet/Elektroniska Kretsar och SystemLinköpings universitet/Tekniska fakulteten

    Författare :Jimmy Johansson; [2017]
    Nyckelord :Folded-Cascode; Settling Time; Settling Time Reduction; Slew Rate; Slew Rate Enhancement; Operational Amplifier; Recycling Folded-Cascode; 180 nm CMOS; Test Buffer; Power-Efficient; Single-Stage Amplifier; Linear Settling Period; Slewing Period;

    Sammanfattning : Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. LÄS MER

  2. 2. Design of a Low Power Cyclic/Algorithmic Analog-to-Digital Converter in a 130nm CMOS Process

    Master-uppsats, Linköpings universitet/ElektroniksystemLinköpings universitet/Tekniska högskolan

    Författare :Ajith kumar Puppala; [2012]
    Nyckelord :Redundant Signed Digit; Correlated level Shifting; Low power; High Speed; Folded cascode;

    Sammanfattning : Analog-to-digital converters are inevitable in the modern communication systems and there is always a need for the design of low-power converters. There are different A/D architectures to achieve medium resolution at medium speeds and among all those Cyclic/Algorithmic structure stands out due to its low hardware complexity and less die area costs. LÄS MER

  3. 3. High-Speed Hybrid Current mode Sigma-Delta Modulator

    Master-uppsats, Linköpings universitet/Linköpings universitet/ElektroniksystemTekniska högskolan; Linköpings universitet/Linköpings universitet/ElektroniksystemTekniska högskolan

    Författare :Balakumaar Baskaran; Hari Shankar Elumalai; [2012]
    Nyckelord :Current mode Sigma Delta Modulator; Leslie-Singh Architecture; Switched Current Integrator; Folded Cascode Integrator; Current mode Flash ADC; High Speed Latched Comparator; Cascode Current Mirrors;

    Sammanfattning : The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. LÄS MER

  4. 4. On the Design of an Analog Front-End for an X-Ray Detector

    Master-uppsats, Linköpings universitet/Institutionen för systemteknik

    Författare :Farooq ul Amin; [2009]
    Nyckelord :Readout Electronics; CMOS Analog Front-End; Low Power; Low Noise; Charge Sensitive Amplifier CSA ; Gm-C Filter; Pole-Zero cancellation circuit;

    Sammanfattning : Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible. LÄS MER

  5. 5. Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology

    Uppsats för yrkesexamina på grundnivå, Linköpings universitet/Institutionen för systemteknik

    Författare :Erik Säll; [2002]
    Nyckelord :Electronics; track-and-hold; CMOS; 0.18; low power; high performance; 10-bit; folded cascode; switch theory; correlated double sampling; CDS; fully differential; gain boosting; regulated cascode; transmission gate; transmission gate switch; clock generator; clock driver; bias; bias circuit; amplifier design; switch design; common mode feedback; CMFB; 80MSPS; 80MS s; Elektronik;

    Sammanfattning : This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. LÄS MER