Sökning: "fpga design workflow"

Hittade 5 uppsatser innehållade orden fpga design workflow.

1. 1. FPGA implementation of an sEMG classifier

   Master-uppsats, Lunds universitet/Avdelningen för Biomedicinsk teknik

   Författare :William Marnfeldt; [2022]
   Nyckelord :electromyography; convolutional neural networks; classifier; field programmable gate array; prosthetic hand; Technology and Engineering;

   Sammanfattning : This master’s thesis discusses the implementation of a convolutional neural network on a Field Programmable Gate Array (FPGA). It deals with implementation be describing a tool chain, starting with the designing of a model in Keras, transforming the model to Hardware Descriptive Language, and finally implementing it on an FPGA. LÄS MER

3. 2. Machine Learning for Space Applications on Embedded Systems

   Master-uppsats, Luleå tekniska universitet/Rymdteknik

   Författare :Ric Dengel; [2021]
   Nyckelord :Machine Learning; Space Application; Embedded System; Hardware Acceleration; FPGA;

   Sammanfattning : As space missions continue to increase in complexity, the operational capabilities and amount of gathered data demand ever more advanced systems. Currently, mission capabilities are often constrained by the link bandwidth as well as onboard processing capabilities. LÄS MER

4. 3. Implementation of a Deep Learning Inference Accelerator on the FPGA.

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Shenbagaraman Ramakrishnan; [2020]
   Nyckelord :Artificial Intelligence; Machine Learning; Deep Learning; Neural Networks; Deep Learning Accelerators; NVDLA; FPGA; Technology and Engineering;

   Sammanfattning : Today, Artificial Intelligence is one of the most important technologies, ubiquitous in our daily lives. Deep Neural Networks (DNN's) have come up as state of art for various machine intelligence applications such as object detection, image classification, face recognition and performs myriad of activities with exceptional prediction accuracy. LÄS MER

5. 4. Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments

   Uppsats för yrkesexamina på avancerad nivå, Luleå tekniska universitet/Institutionen för system- och rymdteknik

   Författare :Carl Bäck; [2020]
   Nyckelord :HLS; System Generator for DSP; Histogram; Xilinx Zynq UltraScale ; FPGA design workflow; Hardware Description Language Coder; HDL Coder; Field Programmable Gate Arrays; Image processing;

   Sammanfattning : FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. LÄS MER

7. 5. Performance Evaluation of MathWorks HDL Coder as a Vendor Independent DFE Generation

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Elisabeth Pongratz; Roshan Cherian John; [2019]
   Nyckelord :MATLAB; Simulink; HDL Coder; XSG; DSPB; Technology and Engineering;

   Sammanfattning : This thesis aims to evaluate MathWorks HDL (Hardware Descriptive Language) Coder and compare the results with designs produced by its vendor dependent counterparts. The focus is mainly on evaluate the design effort needed to close timing and to get optimal resource mapping for a selected design. LÄS MER