Sökning: "hardware description language"
Visar resultat 1 - 5 av 55 uppsatser innehållade orden hardware description language.
1. FPGA programming with VHDL : A laboratory for the students in the Switching Theory and Digital Design course
Kandidat-uppsats, Högskolan i HalmstadSammanfattning : This thesis aims to create effective and comprehensive learning materials for students enrolled in the Switching Theory and Digital Design course. The lab is designed to enable students to program an FPGA using VHDL in the Quartus programming environment to control traffic intersections with sensors and traffic signals. LÄS MER
2. Wordlength inference in the Spade HDL : Seven implementations of wordlength inference and one implementation that actually works
Master-uppsats, Linköpings universitet/Institutionen för systemteknikSammanfattning : Compilers, complex programs with the potential to greatly facilitate software and hardware design. This thesis focuses on enhancing the Spade hardware description language, known for its user-friendly approach to hardware design. LÄS MER
3. Content assist in integrated development environments for hardware description languages
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : Content assist is one of the most powerful features in integrated development environments (IDE). While a lot of research papers exist on content assist for software programming languages (SPL), hardware description languages (HDL) aren’t covered at all. LÄS MER
4. Low-power Acceleration of Convolutional Neural Networks using Near Memory Computing on a RISC-V SoC
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : The recent peak in interest for artificial intelligence, partly fueled by language models such as ChatGPT, is pushing the demand for machine learning and data processing in everyday applications, such as self-driving cars, where low latency is crucial and typically achieved through edge computing. The vast amount of data processing required intensifies the existing performance bottleneck of the data movement. LÄS MER
5. Offloading Workloads from CPU of Multiplayer Game Server to FPGA : SmartNIC implementation with UDP Communication
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : For multiplayer games, the performance of the server’s Central Processing Unit (CPU) is the main factor that limits the number of players on the server at the same time. Compared with the CPU, the Field-Programmable Gate Array (FPGA) architecture has no instructions set and no shared memory. LÄS MER