Sökning: "hardware resource mapping"

Visar resultat 1 - 5 av 7 uppsatser innehållade orden hardware resource mapping.

1. 1. Runtime control for application failure prevention in resource-constrained devices

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Javier Albert Smet; [2022]
   Nyckelord :failure prevention; runtime control; resource-constrained devices; cross-layer optimization; felförebyggande; körtidskontroll; resursbegränsade enheter; optimering över flera lager;

   Sammanfattning : In the last decades, there has been a growing interest towards new use cases in the Internet of Things (IoT) domain, such as extended reality glasses, unmanned aerial vehicles (UAVs), and autonomous driving. The technological advancement observed in such scenarios has also been enabled by the increasing capabilities of small form factor devices. LÄS MER

3. 2. Cross-layer optimization for visual-inertial localization on resource-constrained devices

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Sandra Hernandez Herrero; [2021]
   Nyckelord :;

   Sammanfattning : Mobile devices are increasingly expected to support high-performance cyber- physical applications in resource-constrained devices, such as drones and rovers. However, the gap between hardware limitations of these devices and application requirements is still prohibitive – conflicting goals such as robust, accurate, and efficient execution must be managed carefully to achieve acceptable operation. LÄS MER

4. 3. Mapping HW resource usage towards SW performance

   Magister-uppsats, Mälardalens högskola/Akademin för innovation, design och teknik

   Författare :Benjamin Suljevic; [2019]
   Nyckelord :cache memory; hardware resources; software performance; hardware resource mapping;

   Sammanfattning : With the software applications increasing in complexity, description of hardware is becoming increasingly relevant. To ensure the quality of service for specific applications, it is imperative to have an insight into hardware resources. LÄS MER

5. 4. Performance Evaluation of MathWorks HDL Coder as a Vendor Independent DFE Generation

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Elisabeth Pongratz; Roshan Cherian John; [2019]
   Nyckelord :MATLAB; Simulink; HDL Coder; XSG; DSPB; Technology and Engineering;

   Sammanfattning : This thesis aims to evaluate MathWorks HDL (Hardware Descriptive Language) Coder and compare the results with designs produced by its vendor dependent counterparts. The focus is mainly on evaluate the design effort needed to close timing and to get optimal resource mapping for a selected design. LÄS MER

7. 5. BENCHMARK OF TRIGGERED INSTRUCTION BASED COARSE GRAINED RECONFIGURABLE ARCHITECTURE FOR RADIO BASE STATION

   Master-uppsats, KTH/Skolan för informations- och kommunikationsteknik (ICT)

   Författare :Yu Yang; [2014]
   Nyckelord :;

   Sammanfattning : Spatially-programmed architectures such as FPGA are among the most prevailing hardware in various application areas. However FPGA suffers from great overheads such as area, latency and power efficiency. Coarse-grained Reconfigurable Architecture (CGRA) is designed in order to compensate these disadvantages of FPGA. LÄS MER