Sökning: "time-to-digital"

Visar resultat 1 - 5 av 14 uppsatser innehållade ordet time-to-digital.

1. 1. A Digital Phase-Locked Loop for Frequency Synthesis using an Adaptive Pulse Shrinking TDC

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Viktor Lewin; [2023]
   Nyckelord :Phase-locked loop; PLL; DPLL; Frequency Synthesis; TDC; PFD; Technology and Engineering;

   Sammanfattning : This thesis investigates a new type of Phase-Locked Loop (PLL) architecture which combines a phase/frequency detector (PFD) and a digital loop filter. The quantization is done by a time-to-digital converter which continuously shrinks the pulse coming from the PFD and registers how far it propagates. LÄS MER

3. 2. A digital integer-N PLL architecture using a pulse-shrinking TDC for mmWave applications.

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Simon Richter; [2023]
   Nyckelord :Phase-locked-loops; All-digital Phase-locked-loops; Time-to-digital converters; 5G and beyond; Radio-frequency design; Fas-låsd-loop; Helt-digital fas-låst-loop; Tid-till-digital-omvandlare; 5G och framtiden; Radio-frekvens design;

   Sammanfattning : With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. LÄS MER

4. 3. Fast Clock Synchronization for Large-Scale MEMS Ultrasonic Transducer Arrays

   Master-uppsats, Linköpings universitet/Institutionen för systemteknik

   Författare :Karl-Johan Karlsson; [2022]
   Nyckelord :clock synchronization; clock deskew; MEMS transducer; Delay line; Time-to-Digital conveter;

   Sammanfattning : In many systems today sensors or transmitters need to be read or controlled simultaneously. This thesis investigates a new architecture used for deskewing clock signals between multiple separated parts of a signal transmission system. LÄS MER

5. 4. A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction

   Master-uppsats, Linköpings universitet/Datorteknik

   Författare :Engström Sven; [2020]
   Nyckelord :time-to-digital; time-to-digital converter; TDC; 1.8 ps; field-programmable gate array; FPGA; 20 nm; Xilinx; Kintex; UltraScale; tapped delay line; TDL; taps; carry-chain; ones-counter; bit-counter; bubbles; wave-union; embedded; temperature correction;

   Sammanfattning : This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution. LÄS MER

7. 5. Kompenseringsalgoritm för löptidsmätande laseravståndsmätare baserad på Time to Digital Converter

   M1-uppsats, Karlstads universitet/Fakulteten för hälsa, natur- och teknikvetenskap (from 2013)

   Författare :Jimmy Du; [2019]
   Nyckelord :TOF; TWE; Timing Walk Error; Time-Of-Flight;

   Sammanfattning : This bachelor thesis has been collaborated with Saab Dynamics AB in Karlskoga. The purpose is to analyze time-based rangefinder based on Time-to-Digital Converter with short laser pulses. Compensation will be produced for timing walk-error that is introduced by a dynamic problem. LÄS MER