Sökning: "verilog"

Visar resultat 1 - 5 av 50 uppsatser innehållade ordet verilog.

1. 1. Novel Method of ASIC interface IP development using HLS

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Anestis Athanasiadis; Chandranshu Mishra; [2023]
   Nyckelord :High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

   Sammanfattning : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. LÄS MER

3. 2. Exploring Ethernet Switching Architectures for Area-Efficient Low-End Switches

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Jon Swedberg; Felix Ghosh; [2023]
   Nyckelord :Ethernet Switch; Architecture; Silicon Area; Area Optimization; ASIC; FPGA; Technology and Engineering;

   Sammanfattning : The aim of this thesis project has been to develop an architecture for L2 ethernet switches that would be optimized for silicon area, targeting smaller low-end switches. A selection was made of three different switching architectures, which were compared and analyzed to explore the benefits and drawbacks of different approaches. LÄS MER

4. 3. High Level Synthesis for ASIC and FPGA

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Malin Heyden; [2023]
   Nyckelord :HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

   Sammanfattning : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. LÄS MER

5. 4. Exploiting Spatial Redundancy and Approximate Computing for Area Efficient Image Compression

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Saurav Arjun; [2022]
   Nyckelord :Image Compression; VLSI; Spatial redundancy; DCT; Compression; System Verilog; Technology and Engineering;

   Sammanfattning : Owing to the intensive computation involved in the Discrete Cosine Transform during image com- pression, the design of the efficient hardware architectures for fast computation of the transform has become imperative, especially for real-time applications. Although fast computation techniques have been able to minimise the hardware computation complexity to a certain limit, they could further extend the research to figure out the interesting approaches which can be implemented on applications where power, speed and area are crucial factors to determine the performance of the system. LÄS MER

7. 5. D-band Power Amplifiers in Vertical InGaAs Nanowire MOSFET Technology for 100 Gbps Wireless Communication

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Patrik Blomberg; Ludvig Pile; [2022]
   Nyckelord :D-band; Power Amplifier; Pseudo-differential common source; Stacked; Vertical InGaAs nanowire; MOSFET; Technology and Engineering;

   Sammanfattning : Two different topologies of power amplifiers (PAs) are designed in the frequency range 130-174.8 GHz for use in backhaul transmitters. These are the pseudo-differential common source (PDCS) and the single-ended stacked amplifier topologies. LÄS MER