Sökning: "vhdl verilog"

Visar resultat 1 - 5 av 12 uppsatser innehållade orden vhdl verilog.

1. 1. Novel Method of ASIC interface IP development using HLS

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Anestis Athanasiadis; Chandranshu Mishra; [2023]
   Nyckelord :High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

   Sammanfattning : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. LÄS MER

3. 2. High Level Synthesis for ASIC and FPGA

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Malin Heyden; [2023]
   Nyckelord :HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

   Sammanfattning : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. LÄS MER

4. 3. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Tor Hammarbäck; Jorge Deza Concori; [2022]
   Nyckelord :Technology and Engineering;

   Sammanfattning : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. LÄS MER

5. 4. Design space exploration using HLS in relation to code structuring

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Debraj Das; [2022]
   Nyckelord :Design Space Exploration DSE ; High level Synthesis HLS ; Design Methodology;

   Sammanfattning : High Level Synthesis (HLS) is a methodology to translate a model developed in a high abstraction layer, e.g. C/C++/SystemC, that describes the algorithm into a Register-Transfer level (RTL) description like Verilog or VHDL. LÄS MER

7. 5. Customized Processor Design for 5G Data Link Layer Processing

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Patric Wargéus; Lukas Forsberg; [2020]
   Nyckelord :Technology and Engineering;

   Sammanfattning : This thesis aims to explore the workflow related to designing an application specific instruction-set processor (ASIP). An ASIP is a processor similar to a hardware accelerator (HAC) in terms of performance and efficiency, but containing elements of general purpose processors (GPPs) when it comes to programmability and flexibility. LÄS MER