Evaluation of Cryptographic CRC in 65nm CMOS

Sammanfattning: With the rapid growth of Internet-of-Things (IoT), billions of devices are expected to be interconnected to provide various services appealing to users. Many devices will get an access to valuable information which is likely to increase the number of malicious attacks on these devices in the future. Therefore, security is considered as one of the most critical challenges in the development of IoT. In order to secure resource-constrained devices such as sensors or radio frequency identification (RFID) tags which form the backbone of IoT, lightweight cryptographic algorithms are required. This thesis focuses on the problem of message authentication. To authenticate a message means to verify that the message: (1) comes from the right sender (i.e. its authenticity), and (2) has not been modified (i.e. its integrity). It is challenging to use traditional message authentication methods in resource-constrained devices because typically they can allocate only a few hundred gates for implementing security due to their limited computing, storage and energy resources. To address these needs, a new message authentication algorithm based on a Cryptographic Cyclic Redundancy Check (C-CRC) was developed by KTH in collaboration with Ericsson. In this thesis, we implemented C-CRC and compared it with KECCAK Message Authentication Code (KMAC) standardized by the National Institute of Standards and Technology (NIST) in 2016. First, MATLAB and Verilog versions were developed for both algorithms. The comparison of these two versions allowed us to verify the correctness of algorithms functionality. After that, the Verilog descriptions were simulated in ModelSim and synthesized using Synopsys design compiler. Finally, placement and routing was performed using Cadence SoC Encounter. The evaluation results show that C-CRC outperforms KMAC in terms of area, power, throughput per area, and energy per bit. However, C-CRC is worse than KMAC in terms of latency. We have also investigated several different options of implementing C-CRC, including producing more than one bit of output per clock cycle. We found that such a technique improves throughput of C-CRC with the minimal penalty in area and power consumption