Hardware Accelerator of Matrix Multiplication on FPGAs : Hardware Accelerator of Matrix Multiplication on FPGAs

Sammanfattning: To solve the computational complexity and time-consuming problem of large matrix multiplication, this thesis design a hardware accelerator using parallel computation structure based on FPGA. After function simulation in ModelSim, matrix multiplication functional modules as a custom component used as a coprocessor in co-operation with Nios II CPU by Avalon bus interface. To analyze computation performance of the hardware accelerator, two software systems are designed for comparison. The results show that the hardware accelerator can improve the computational performance of matrix multiplication significantly.