Exploiting Spatial Redundancy and Approximate Computing for Area Efficient Image Compression

Sammanfattning: Owing to the intensive computation involved in the Discrete Cosine Transform during image com- pression, the design of the efficient hardware architectures for fast computation of the transform has become imperative, especially for real-time applications. Although fast computation techniques have been able to minimise the hardware computation complexity to a certain limit, they could further extend the research to figure out the interesting approaches which can be implemented on applications where power, speed and area are crucial factors to determine the performance of the system. This thesis work is an attempt towards implementing a novel approach to provide image com- pression with low area and power requirement . Various reduced computational compression algo- rithms were proposed by exploiting hardware efficient image compression algorithms. Furthermore, to understand and compare their performances, the concepts of spatial redundancy and approxi- mate computing in images are exploited. The work designs a number of hardware efficient image compression algorithms. In this thesis work, the models try to group the pixel data by taking the image’s feature space similarity and spatial coherence characteristics into consideration. These models have been tested successfully on a wide range of images, including black and white images and coloured images. The proposed architectures in this paper bring forth equal or higher image performance with higher compression ratio with less hardware requirement. These architectures are also compared among each other to provide an understanding on design-space exploration.