Global clock distribution in the SiLago platform

Sammanfattning: The extreme evolution of Very Large Scale Integration (VLSI) design has followed Moore’s law for the past decades, which predicts a doubling of the number of transistors that can be implemented on a chip every 18 months. However, tightly coupled with the evolution of the technology capabilities, the complexity during the implementation of such designs has also increased dramatically. Several solutions have been proposed to cope with this problem, one of them being currently developed at the group of VLSI design at KTH named the SiLago platform.The SiLago platform is a framework that enables an efficient VLSI design methodology by providing a set of tools and libraries capable of generating ready-to-manufacture Aplication Specific Integrated Circuit (ASIC) designs from a high level description. The physical design of a SiLago design is achieved using pre-characterized, hardened, abuttable, micro-architectural blocks that are placed during the synthesis process.This design methodology causes a set of problems to arise, one of them being the distribution of a valid clock signal that reaches all the sinks. Given the nature of the designs that the SiLago platform intends to tackle a fully synchronous design style can be considered impractical and unachievable so alternative approaches and methods had to be taken.This work proposes a methodology for distributing a valid clock signal through the global Network-on-Chip (NoC) on a SiLago design. By analysing the timing paths in each every of the NoC edges a set or rules is derived from standard Static Timing Analysis (STA) methods. Additionally, by using a previously developed GALS-related interface type, named GloballyRatiochronous Locally-Synchronous (GRLS), the distribution methodology can cope with latency insensitive paths as well as allowing a fine grain frequency scaling in different SiLago regions.