Hardware Implementation of a 32-point Radix-2 FFT Architecture

Sammanfattning: The Fast Fourier Transform (FFT) algorithm has been widely used in the Digital Signal Processing industry as a rudimentary operation to select the specific frequency components of a signal, which has been involved with other time domain signals. In order to fulfill the requirements of executing precise calculations and less power & area consumption, an algorithm with less number of adders and multipliers is used. In this thesis, a radix-2 32-point FFT algorithm, which is using Decimation- In-Frequency (DIF) , is implemented in VHDL. In addition, the implementation is designed for a 65nm CMOS process. The ASIC verification process is tested and implemented, by using Synthesis, Post-synthesis Simulation, Place & Route, Post-layout Simulation, and Prime Time. Results regarding area, throughput, and power consumption are presented.