A Camera System for the KTH MIST Satellite

Sammanfattning: The KTH MIST satellite will include a Camera System that should capture pictures of Earth from Space. Due to low Bandwidth, the satellite can traverse several lapses around the Earth until the picture is transmitted down to Earth. The picture is processed and the raw pixels stored in an on-board DRAM. A problem is that pixel-data is subjected to bit-flips because FPGAs and DRAMs in general are sensitive to ionizing radiation which can corrupt data. This will degrade the performance of the system, unless some protective measures are taken. The Camera System is connected to the Single Event Upset Detector (SEUD) experiment, so that the SEUD experiment will have something to compute while waiting for SEU events to happen. Another important topic in this research is the power consumption, i.e., how much power will the Camera System consume, and how can it be minimized. The goal is to find the most power consuming areas in the block design and optimize it. The self-healing SEUD architecture consist of two COTS FPGAs, one ARTIX- 7 and one SmartFusion2 chip. The ARTIX-7 chip is sensitive to radiation, and is used as a sensor-platform for capturing SEUs as bit-flips happens in its configuration memory. The SmartFusion2 chip, on the other hand, is less sensitive to radiation due to its flash-ram based configuration memory. It also contains an ARM Cortex-M3, and is used to supervise and perform tasks like re-programming, restarting and overseeing the ARTIX-7 chip, as well as storing images and communicating with the main On-Board Computer (OBC) of the MIST satellite. Pictures are stored in a local DRAM memory that is protected from SEUs through Triple Modular Redundancy (TMR) and scrubbing. In this thesis, an OV7670 camera module is used for capturing pictures and save it in a local memory. Two camera system implementations are investigated and implemented using the Nexys Video board as a target platform. The 2nd Camera System fulfills the throughput and generates 640x480x3 = 921.6 kB pixels per frame. The pixel stream is forwarded by a VDMA unit to other components for storage or further processing. The setup has been validated through simulations and by connecting the VDMA to HDMI and VGA screens. The implementation had a total on-chip power consumption of 1.172 W (including the MicroBlaze processor), while the I/O used for debugging consumed 0.3 W (29 percent of the total power consumption). Hence, the power consumption of the final Camera System is below 1 W, which is the power budget allotted for the whole SEUD experiment. A combination of RTL code along with AXI4 compliant IPs was concluded to be the best choice for the 2nd Camera System.