High-Level Synthesis for Efficient Design and Verification

Sammanfattning: Designing hardware using High Level Synthesis automates parts of the digital hardware design process. By automating the process control is passed from the designer to the tool, thus it is highly important that the tool generates high performance hardware in terms of area and speed. This thesis explores the tool performance of Vivado HLS using two designs implemented anew with High Level Synthesis and Hardware Description Language. The evaluations are done based on hardware performance and functional verification times and how these scale to larger designs. When using High Level Synthesis one should have a good idea of what hardware that is ideal for the given design in order to design high performance hardware. The synthesis process of generating Register Transfer Level-code from C or C++ is highly dependent on syntax, especially as designs grow larger. This could be satisfied by having a good balance of pre-defined libraries and design specific code and keeping native C data types for high functional verification speed. There are different ways of designing using High-Level Synthesis this thesis aims to explore these and highlight their pros and cons. Thus providing guidelines and ideas for how to work with High-Level Synthesis in different situations.