Design of a 16 GSps RF Sampling Resistive DAC with on-chip Voltage Regulator

Sammanfattning: Wireless communication technologies continue to evolve to meet the demand for increased data throughput. To achieve higher data throughput one approach is to increase the bandwidth. One problem related to very large bandwidths is the implementation of digital-to-analog converters with sampling rates roughly in the 5 to 20 GHz range. Traditionally, current-steering data converters have been the go-to choice but their linearity suffers at higher frequencies. An alternative to the current-steering digital-to-analog converter is the voltage-mode digital-to-analog converter, which is an attractive option for integration into digital intensive application-specific integrated circuits due to its digital-in-nature architecture. In this thesis, a resistive voltage-mode digital-to-analog converter with an integrated low-dropout voltage regulator is proposed for a sampling rate of 16 GSps. The proposed resistive voltage-mode digital-to-analog converter with an output impedance matched to a 100 Ω load, achieves a spurious-free dynamic range of 64 dBc and intermodulation distortion of 66 dBc for output frequencies up to 5.5 GHz in the worst process corner.