Offloading Workloads from CPU of Multiplayer Game Server to FPGA : SmartNIC implementation with UDP Communication

Sammanfattning: For multiplayer games, the performance of the server’s Central Processing Unit (CPU) is the main factor that limits the number of players on the server at the same time. Compared with the CPU, the Field-Programmable Gate Array (FPGA) architecture has no instructions set and no shared memory. Offloading some tasks from the CPU to the FPGA may help the CPU improve processing efficiency. This thesis explores which tasks on a CPU can be offloaded to a FPGA and how to design such a circuit system. The performance of the developed system also needs to be measured. We decided to offload communication tasks and data processing tasks to an FPGA. The result is that the FPGA server is available for work, the maximum number of users is 80, and the maximum network latency is 30-40 ms. The most important result is that a FPGA can be used as a multi-player server. One of the severe limitations of this design is the number of hardware resources. A 7-series FPGA is divided into several similar clock regions, which means the number of Flip Flop (FF)s near the same clock edge is fixed. If adding more FFs in the same component, the routing delay can not meet the set-up time requirements. Previously, people used the FPGA as the support accelerator to the server CPU. The CPU still works as a paramount communication link with one or several multi-connection parts and connects to the FPGA via the Peripheral Component Interconnect Express (PCIe) to use the FPGA to process data or pack/unpack Ethernet frames. We have designed and implemented a whole multi-connection server in a Hardware Description Language (HDL) and downloaded the resulting hardware in an FPGA.