Current Distribution in High RF Power Transistors

Sammanfattning: To obtain the power levels required from high RF power transistors, the size of the chip has often to be made so large that inductance of electrical connections inside the package cannot be neglected. This may have the effect that various parts of the transistor chip are not connected exactly parallel, i.e. drain and gate voltages and currents densities will not be the same on different parts of the chip. This may result in degraded output power and efficiency. The same effect may occur when more than one chip are connected in parallel in a transistor package to obtain even higher output power.Often the connections to the transistor package are approximated as a number of electrical point connections (normally three: gate, drain, source); meaning that each of them can be described by a single electrical potential and current. In reality, they may be large enough that voltage and current distributions have to be considered. These distributions will be affected by different mountings of the transistor and other connected components.In this work, the LDMOS power transistor MRF6S21140HR3 was modeled using the segmentation method in high frequency signal simulation HFSS which is a 3D Full-Wave Electromagnetic Field Simulation, and utilized the advanced design system ADS to find a parameterized lumped model. Both the electromagnetic and lumped models showed consistent results. Non-ideal parallel connection of sub-transistors on chip is very important, but further studies are needed for definite conclusion. It was verified through modeling that non ideal parallel connection of different chips in the package does have an effect; the effect however is quiet small which proves that the signal is slightly non-uniformly distributed between the three chips in the package. External connection to PCB (drain connection is considered in this work) can effectively be taken as a point connection to some approximation. The electrical behavior of the modeled transistor was studied through the design of a class B power amplifier in order to estimate the importance of performance degradation due to non-ideal parallel connections and how these non ideal connections degrade efficiency and output power. The modeled transistor can deliver a maximum output power of 147 watts and efficiency of 65%. We have also studied the current distribution between the three chips in a three stage class B power amplifier. Again, the difference in the current distribution between the three chips turned out to be quiet small. All these results are presented through this work. The final conclusion regarding the current distribution between multichips cannot be made just based on these simulation results. The next step should be aimed at considering other effects, the thermal effect for example, in order to know exactly whether it is uniformly or not uniformly distributed.