A Technology Agnostic Approach for Standard-cell Layout Design Automation

Sammanfattning: The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly contains millions of standard cells. The sheer amount implies that even small optimizations on a standard cell can have a significant effect on the SoC performance. To ensure the performance of standard cells, many of these are hand-drawn. This is a tedious task that needs to be done every time a new process technology emerges. Something which requires both many man-hours and that holds a risk of designing sub-optimal solutions or introducing human error into the design. Presented in this thesis is a method for automatizing the complete design process of standard cell layouts, requiring only a netlist and a few fundamental design rules for the given technology. The overall procedure was divided into three parts: placement, routing, and evaluation. The tool is entirely built in Python and for functionality verification commercial EDA tools from CadenceTM were used. The generated standard cells have shown to match the area requirements of typical industry-level standard cells and in some critical complex cells even outperform them.