Arbitrary Decimation for High Sample Rates, Algorithm Design and FPGA implementation

Sammanfattning: This master thesis investigates how to perform irrational decimation, the process of reducing the sample rate of a signal, for high throughput systems. The thesis work consists both an algorithmic part and an implementation part. In the algorithmic part, an algorithm that could cope with the requirements is found, and investigated due to different aspects. A group of filters that are investigated further are different version of the so called farrow structure. The farrow structure can be used in a lot of different applications but the interesting thing here is that decimation can be made, quite arbitrary, while all parameters of the structure are kept static, aside from one control parameter that must be recalculated for every sample. The result of the algorithm investigation is an algorithm that consists of a transposed farrow filter in series with a fixed halfband filter. The series connection of the two different filters were found to be necessary to cope with the given requirements of the project. Especially the requirements on the stopband attenuation (80 dB) and passband ripple (0.02 db) in combination with the bandwidth (80%), mad it impossible to use just a farrow filter without using too high filter orders. Both the transposed farrow structure and the halfband filter can be implemented, using high levels of parallelization, which was necessary in the implementation phase, to be able to match the high throughput demands. During the implementation part, the algorithm is implemented onto a FPGA, a Xilinx Virtex Ultrascale. The implementation aims towards proving that the algorithm could be used for high throughput applications and is implemented in 8 parallel at a clock speed of 312.5 MHz. The parallelization in combination with the clock speed gives the implementation a capacity of decimating an incoming signal at a sample rate of 2.5 GSa/s. To solve the problem of the multiple data rates within the implementation, a shift register is used to only execute the main parts of the implementation when all parallelization branches have valid data at their inputs. This transforms almost all the problem with the multirate system to a much simpler data driven implementation. The decimation factor can be selected from 2 and upwards with a certain resolution. The resolution is higher for smaller decimation factors than for larger ones.