Power-Aware Software Development For EMCA DSP

Detta är en Master-uppsats från KTH/Skolan för informations- och kommunikationsteknik (ICT)

Författare: Meishenglan Zhang; [2017]

Nyckelord: ;

Sammanfattning: The advent of FinFET technology necessitates a shift towards early dynamic power awareness, not only for ASIC block designers but also for software engineers that develop code for those blocks. CMOS dynamic power is typically reduced by optimizing the RTL models in terms of switching activity and clock gating efficiency. There is not much to be done after a model is committed. Programmable blocks though, like the Phoenix 4 Digital Signal Processor(EMCA Ericsson Multi Core Architecture), can have a “second chance” for low power even after silicon is produced by efficient use of the software source code in order to impact the dynamic power metrics. This requires a "full-stack" of power awareness all the way from the DSP hardware model up to the software development IDE. This Thesis work aims at two goals. The first goal is to realize a prototype, encapsulated flow for the DSP software developers which connects software IDE entry point to the low level, complex hardware power analysis tools. The second goal is to demonstrate how software can be used as an auxiliary knob to exploit potential tradeoffs in order to improve the DSP's dynamic power metrics. This hypothesis is tested by rescheduling operations on the DSP's resources either manually or implicitly through the compiler. Moreover, a method to align and compare algorithms, when it is possible to tradeoff performance for power, is devised and the estimation results are compared against real silicon measurements. The results show that the developed analysis flow is reliable and very efficient for the given purpose, even for people who have limited knowledge about low level hardware to facilitate quick power exploration and profiling. This is mainly realized by a unique feature that associates specific lines in the source code with the toggling behavior of the hardware model while execution. Based on that, the tradeoffs between power and performance for several testcases are demonstrated at both the assembly and C levels with good correlation versus silicon. Overall, this work's outcome hints that the compiler and software teams have many options to consider in order to optimize dynamic power for products already in the field.

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