Investigation of Resistive Random Access Memory for 1T1R Nanowire Array Integration

Sammanfattning: As modern electronics have started to reach its physical scaling limits, novel architectures and physics is needed to meet future demands. Oxide-based Resistive Random Access Memory (RRAM) is a new emerging technology that uses filament formation and rupture in thin oxides to generate resistive switching. Structure of RRAM devices often use transistors as selector devices. In this work a one-transistor-one-RRAM (1T1R) device is characterised using pulsed measurements. The endurance of the device is extracted as well as the switching probability. Moreover, the data acquired from the device is used to simulate 1T1R nano-wire (NW) arrays by integrating a cell level small signal model with an array-level model. Analytical expressions are used to calculate parasitic capacitances. Worst-case cell analyses of the access voltage and read margin are performed for different pulse widths, resistivities and technology nodes. The average switching probabilities for a given array size are also calculated using experimental data. It turns out that the examined device showed excellent endurance, exceeding 2 million cycles. Moreover, it also showed excellent switching characteristics and resistance window. Simulations showed that high probability of switching could be achieved even for array sizes > 1000 bits. These results show that it is possible to integrate > Mbit sub-arrays with low-voltage 10 ns pulses, providing a foundation for larger Gbit memory sizes, which are comparable with current DRAM and NAND technology.