FPGA Co-Processing in Software-Defined Radios
Sammanfattning: The Internet of Things holds great promises for the future. In the smart cities of tomorrow, wireless connectivity of everyday objects is deemed essential in ensuring efficient and sustainable use of vital, yet limited resources such as water, electricity and food. However, radio communication at the required scale does not come easily. Bandwidth is yet another limited resource that must be used efficiently so that wireless infrastructure for different IoT applications can coexist. Keeping up with the digitalization of modern society is difficult for wireless researchers and developers. The Software-Defined Radio (SDR) is a technology that allows swift prototyping and development of wireless systems by moving traditional hardware-based radio building blocks into the software domain. For developers looking to be on the bleeding edge of wireless technology, and thus keep up with the rapid digitalization, the SDR is a must. Many SDR systems consist of a radio peripheral that handles tasks such as amplification, AD/DA-conversion and resampling that are common to all wireless communication systems. The application-specific work is done in software at the baseband or an intermediate frequency by a host PC connected to the peripheral. That may include PHY-related processing such as the use of a specific modulation scheme as well as higher-layer tasks such as switching. While this setup does provide great flexibility and ease-of-use, it is not without its drawbacks. Many communication protocols specify a so-called round-trip time and devices wishing to adhere to the protocol must be able to respond to any transmission within that time. The link between the host and the peripheral is a major cause of latency and limits the use of many software-defined radio systems to proof-of-concept implementations and early prototyping since it prevents the round-trip time from being fulfilled. Overcoming the latency in the link would allow the flexibility of SDRs to be brought into field applications.This thesis aims to offload the link between the host PC and the radio peripheral in a typical SDR system. Selected parts IEEE 802.15.4, a wireless standard designed for IoT applications, were implemented by using unused programmable logic aboard the peripheral as a co-processor in order to reduce the amount of data that gets sent on the link. Frame success rate and round-trip time measurements were made and compared to measurements from a reference design without any co-processing in the radio peripheral. The co-processing greatly reduced traffic on the link while achieving a similar frame success rate as the reference design. In terms of round-trip time, the co-processing actually caused the latency to increase. Furthermore, the measurements from the coprocessing system showed a counter-intuitive behavior where the round-trip time decreased as the rate of the generated test frames increased. This unusual behavior is most likely due to internal buffer mechanisms of the operating system on the host PC. Further investigation is required in order to bring down the response time to a level more suitable for field applications.
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