Sökning: "UVM"
Visar resultat 1 - 5 av 8 uppsatser innehållade ordet UVM.
1. Low-power Acceleration of Convolutional Neural Networks using Near Memory Computing on a RISC-V SoC
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : The recent peak in interest for artificial intelligence, partly fueled by language models such as ChatGPT, is pushing the demand for machine learning and data processing in everyday applications, such as self-driving cars, where low latency is crucial and typically achieved through edge computing. The vast amount of data processing required intensifies the existing performance bottleneck of the data movement. LÄS MER
2. Validation of efficiency of formal verification methodology for verification closure
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. LÄS MER
3. Development of a new verification environment for a GPU hardware block using the Universal Verification Methodology
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : The invention of the integrated circuit is a key milestone in the history of electronic circuits. Since its introduction the number of components on a chip have increased rapidly, making them more powerful and able to perform complex operations, but it has also changed the design process. LÄS MER
4. Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register-Transfer Level (RTL) verification. Verification of ASICs is very important nowadays especially in terms of production costs, time to market and the sustainability of products. LÄS MER
5. Exploration of formal verification in GPU hardware IP
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : Today, digital circuits are part of every ones daily life in form of mobile phones, computers, television, smart cards etc. The advent of new technologies such as internet of things, 5G etc. are continuously making the digital circuits more and more complex in design. LÄS MER
