Design of a 13-Bit SAR ADC with kT/C noise cancellation technique

Sammanfattning: One of the main limitations of a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is the large input capacitance needed to achieve the desired performance. This large input capacitance increases the total area of the ADC and it imposes the use of a powerful buffer to drive it. Since the input capacitance is inversely proportional to the kT/C noise, reducing it, generates more noise. To reduce the input capacitance, there is a need to deal with the extra noise generated. In this thesis, a 13-bit SAR ADC at 40MS/s using kT/C noise cancellation has been designed in 65nm technology node. This technique allows for a considerable decrease in the size of the ADC input capacitor without reducing the ADC’s performance, it also reduces the requirements for the input buffers. The designed SAR ADC uses a total input capacitance of 172.8 fF and it achieves an SNR of 67.64 dB before noise cancellation and 74.173 dB after noise cancellation. To achieve similar results without implementing the noise cancellation technique one has to increase the input capacitance by at least 10 times. Hence, there is a need to implement noise cancellation techniques, as using large input capacitance to design SAR ADC increasing the overall area of the design.