Module-level Verification For DRRA and DiMarch

Sammanfattning: This thesis presents a verification process for the electronic hardware design implemented using Very-high-speed integrated circuits Hardware Description Languages (VHDL). In this study, Register Transfer Level(RTL) modules are verified. They belong to Dynamic Reconfigurable Resource Array (DRRA) project and Distributed Memory Architecture (DiMArch) project. Firstly, detailed description and specification of each module provided from designer during implementation of the test. According to the specification, simulation based tests are used as white-box verifications of the modules. Methodology and implementation details for verification of the system are briefly explained. The basic objective of this thesis is finding location of bugs inside the design which improves the implementation of DRRA and DiMArch projects. Results show that all bugs determined during verification have been reported and fixed, leading to a bug-free implementation.