A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools

Sammanfattning: This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. First, a design stage where a golden reference is created in Mathworks' Simulink using different HDL supported toolboxes like the DSP HDL toolbox. Testbenches are created along side the golden reference in Mathworks' environment with Matlab and Simulink. The same testbenches will be used during the entirety of the flow to continuously verify all of the components in each stage. The second stage is the code generation which will be done using another toolbox from Mathworks, the HDL Coder. To verify the code, Cadence's Xcelium will be used together with Mathworks' HDL Verification toolbox to simulate the produced code using the mentioned testbenches, giving the simulation the same stimuli as used for the golden reference. To automate the flow, automation scripts are created to configure, set up and start the different steps of the stages and connecting the Cadence tools to the Mathworks environment, leaving only the system designing left for the developer. As a final step, Cadence's Genus is used to synthesize the system and evaluate the designs cost in terms of area and speed with the use of a 65 nm standard cell library. The HDL Coder generates HDL in a hierarchical, readable and well documented fashion with extended debugging properties. The many settings allow for customization of the generation, both in terms of coding style and in architecture. The quality in terms of design costs lies upon the developer. Even though the many toolboxes with predefined algorithms exists to help the designer, custom control systems do not exist as toolboxes and are not better than its implementation as designed by the creator. Using the Mathworks and Xcelium tools in the same environment allowed to reduce the verification time by reuse of testbenches and automate the design of components for a chip concept like the 5G disruptive digital beamforming circuit for BeammWave.