Investigating the Scalability of Direct-to-Master Caches

Sammanfattning: Upcoming processors will utilize an ever increasing number of transistors bye mploying them as multiple cores. With the growth in number of cores, current cache hierarchies become one of the limiting factors for the scalability of applications utilizing multi-core processors. D2M, a new split cache hierarchy design, provides a unified mechanism for cache searching, eviction, and coherence,that eliminates level-by-level data movement and searches. This work contributesto research on D2M by performing a scalability analysis using High-Performance Computing benchmarks from the SPLASH-2x benchmark suite. By conducting experiments for 2, 4 and 8 cores with the Gem5 full-system simulator, we provide ageneral scalability trend for D2M. The experiments specifically target scalability ofthe metadata hierarchy. MD3 lock granularity and shared region overhead are examined, resulting in a definite number of locks to avoid MD3 lock aliasing for the selected benchmarks. In addition, a detailed performance comparison between D2M and a generic standard cache hierarchy model is given for all core configurations.