Acoarse grain reconfigurable memory architecture for linear algebra and deep neural networks

Sammanfattning: Companies and institutions around the world have been working to develop machines with always more computing power. This race has now found its new objective: hexascale computing (with 1018 flops machines). But high performance computing in not the only application using Very Large Scale Integration (VLSI) and suffering from the end of the Moore’s law. Post-Moore architectures offer a solution to keep increasing the performances of computing systems despites the limitations of Central Processing Unit (CPU) based architectures. A common option is to delegate certain tasks, as Digital Signal Processing (DSP), to highly optimized co-processors named Hardware Accelerators. But such Hardware Accelerators require an expensive engineering effort from their high level specifications to their physical implementation. The SiLago project, develops in KTH a Coarse Grain Reconfigurable Architecture (CGRA) to simplify the implementation of application specific chips. It offers a catalog of computing, memory and control cells ready to be produced on silicon. Using this catalog to build an Application Specific Integrated Circuit (ASIC) would raise the abstraction from the standard gate level to the macro blocks that are the SiLago blocks. This works introduces the architecture of a SiLago based system, and describes its memory architecture called DiMarch (for Distributed Memory architecture). It also proposes some modifications to the memory cells that could add interesting features and enhancement to the memory subsystem.