Sökning: "Delay-Locked Loop"

Hittade 5 uppsatser innehållade orden Delay-Locked Loop.

1. 1. Investigation of Analog Calibration Systems for Spurious Tone Suppression in Frequency Triplers

   Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

   Författare :Cristian Alexandru Ghihanis; Barath Copparam Santhanakrishnan Sudarsan; [2023]
   Nyckelord :Delay-Locked Loop; DLL; Edge-Combining; EC; EC DLL; Edge-Combining Delay-Locked Loop; spurious tone calibration; spurs calibration; spurious tones compensation; spurs compensation; Technology and Engineering;

   Sammanfattning : The market for Wi-Fi receiver designs for latest Wi-Fi standards, that cover RF bands in the 2.4 GHz, 5 GHz and 6 GHz spectrum, require increasingly stringent power consumption limitations as more of the market is driven towards battery-powered devices. LÄS MER

3. 2. DLL Based Reference Multiplier for the use in a PLL for WLAN applications

   Master-uppsats, Lunds universitet/Fysiska institutionen

   Författare :Kamal Gupta; [2015]
   Nyckelord :reference multiplier; Frequency synthesizer; Frequency multiplier; PLL; DLL; Delay locked loop; VCDL; inverter-based VCDL; charge pump; XOR phase detector; phase noise; 4X multiplier; Technology and Engineering;

   Sammanfattning : This master’s thesis project report deals with the design of multiplier for the reference signal to the Phase Locked Loop (PLL) used in WLAN application. The reference multiplier designed is based on a newly proposed architecture of dual loop feedback Delay Locked Loop (DLL) in which multiplication is performed within the loops. LÄS MER

4. 3. A Wide Range Low Power Low Jitter All Digital DLL for Video Applications

   Master-uppsats, Elektroniksystem

   Författare :Yasir Ali Shah; Muhammad Touqir Pasha; [2010]
   Nyckelord :DLL; Digital; Low Jitter; Wide Range;

   Sammanfattning : Technological advancements in video technology have placed stringent requirements on video analog front ends (AFEs) to deliver high resolutions crisp images while consuming low power to deliver optimal performance. One of the vital parts of an AFE is a delay locked loop (DLL). LÄS MER

5. 4. A Sizing Algorithm for Non-Overlapping Clock Signal Generators

   Uppsats för yrkesexamina på grundnivå, Institutionen för systemteknik

   Författare :Fatih Kavak; [2004]
   Nyckelord :Electronics; Non-overlapping clock signal generator circuits; PLL; DLL; CMOS Transistors; Delay models for CMOS circuits; Elektronik;

   Sammanfattning : The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. LÄS MER

7. 5. Delay-locked Loop : an adaptive timing alignment

   Magister-uppsats, Blekinge Tekniska Högskola/Institutionen för signalbehandling

   Författare :Andreas Ericsson; Malena Lindgren; [1996]
   Nyckelord :Delay-locked loop; adaptive timing;

   Sammanfattning : Conventional approches to the problem of extracting a clock from the data do not automatically hold the clock in the center of the data-eye. This thesis describes a data feedback technique that adjusts the clock and significantly reduces timing uncertainty by compensating for initial ciruit misalignment, propagation delay variations and low-frequency jitter. LÄS MER