Sökning: "Code Synthesis"

Visar resultat 1 - 5 av 52 uppsatser innehållade orden Code Synthesis.

  1. 1. Difference Between Memory-based Storage and Register-based Storage on FPGAs

    Master-uppsats, Linköpings universitet/Institutionen för systemteknik

    Författare :Yiqian Cui; [2023]
    Nyckelord :;

    Sammanfattning : Memory-based storage and register-based storage are commonly used storagetypes in fpgas. This thesis aims to build up the architecture of memory-basedstorage and register-based storage, implement the corresponding methods, compare the difference between them and determine which kind of storage workswell under different circumstances. LÄS MER

  3. 2. Code Synthesis for Heterogeneous Platforms

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Zhouxiang Fu; [2023]
    Nyckelord :Code Synthesis; Heterogeneous Platform; Zero-Overhead Topology Infrastructure; Kodsyntes; Heterogen plattform; Zero-Overhead Topologi Infrastruktur;

    Sammanfattning : Heterogeneous platforms, systems with both general-purpose processors and task-specific hardware, are largely used in industry to increase efficiency, but the heterogeneity also increases the difficulty of design and verification. We often need to wait for the completion of all the modules to know whether the functionality of the design is correct or not, which can cause costly and tedious design iteration cycles. LÄS MER

  4. 3. Improving the Synthesis of Annotations for Partially Automated Deductive Verification

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Hovig Manjikian; [2023]
    Nyckelord :Formal verification; Automated verification; Contract inference.; Formell verifiering; Automatiserad verifiering; Kontraktgenerering.;

    Sammanfattning : This work investigates possible improvements to an existing annotation inference tool. The tool is part of a toolchain that aims to automate the process of software verification using formal methods. LÄS MER

  5. 4. Develop a Graphical User Interface for the assembler for SiLago Platform

    Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Författare :Yuxuan Wang; [2023]
    Nyckelord :Graphic intermediate representation; Graphical analytic system; High-level synthesis tool; Grafisk mellanrepresentationen; Grafiskt analytiskt system; Högnivå syntes verktyg;

    Sammanfattning : Vesyla-II is developed as the High-Level Synthesis (HLS) tool serving the SiLago platform. The assembler Manas is a part of the Coarse Grain Reconfigurable Architectures (CGRA) compiler in Vesyla-II, which is used to transform the information from source code into the target language. LÄS MER

  7. 5. High Level Synthesis for ASIC and FPGA

    Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknik

    Författare :Malin Heyden; [2023]
    Nyckelord :HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

    Sammanfattning : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. LÄS MER