Sökning: "RTL simulering"

Hittade 2 uppsatser innehållade orden RTL simulering.

1. 1. Design a Three-Stage Pipelined RISC-V Processor Using SystemVerilog

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Ziyan He; [2022]
   Nyckelord :RISC; RISC-V; ISA; SystemVerilog; RTL simulation; RV32IM; CPI; RISC; RISC-V; ISA; SystemVerilog; RTL simulering; RV32IM; CPI;

   Sammanfattning : RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. LÄS MER

3. 2. Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Weijiang Kong; [2019]
   Nyckelord :LDPC; CGRA; Reconfigurable architecture; VLSI design; ASIC; LDPC; CGRA; Konfigurerbar arkitektur; VLSI design; ASIC;

   Sammanfattning : Low density parity check (LDPC) code is an error correction code that has been widely adopted as an optional error correcting operation in most of today’s communication protocols. Current design of ASIC or FPGA based LDPC accelerators can reach Gbit/s data rate. LÄS MER