Sökning: "RTL simulation"
Visar resultat 1 - 5 av 15 uppsatser innehållade orden RTL simulation.
1. Modeling, Simulation, and Injection of Camera Images/Video to Automotive Embedded ECU : Image Injection Solution for Hardware-in-the-Loop Testing
Uppsats för yrkesexamina på avancerad nivå, Uppsala universitet/Signaler och systemSammanfattning : Testing, verification and validation of sensors, components and systems is vital in the early-stage development of new cars with computer-in-the-car architecture. This can be done with the help of the existing technique, hardware-in-the-loop (HIL) testing which, in the close loop testing case, consists of four main parts: Real-Time Simulation Platform, Sensor Simulation PC, Interface Unit (IU), and unit under test which is, for instance, a Vehicle Computing Unit (VCU). LÄS MER
2. Exploring Ethernet Switching Architectures for Area-Efficient Low-End Switches
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : The aim of this thesis project has been to develop an architecture for L2 ethernet switches that would be optimized for silicon area, targeting smaller low-end switches. A selection was made of three different switching architectures, which were compared and analyzed to explore the benefits and drawbacks of different approaches. LÄS MER
3. Design a Three-Stage Pipelined RISC-V Processor Using SystemVerilog
Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)Sammanfattning : RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. LÄS MER
4. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. LÄS MER
5. Design parameterizable filter using High Level Synthesis
Master-uppsats, Lunds universitet/Institutionen för elektro- och informationsteknikSammanfattning : As the ASIC designs continue to grow in complexity, traditional RTL level of abstraction is becoming a productivity bottleneck. The RTL design process requires extensive time and effort for verification of algorithmic correctness as well as correct timing and interface behavior. LÄS MER