A Low Noise Digitally Controlled Oscillator for a Wi-Fi 6 All-Digital PLL

Sammanfattning: Following the rise of Internet of Things (IoT), or just the technological advancements and expectations in a world where the things are or will be connected, new demands are put on Integrated Circuit (IC) for wireless connectivity. The use cases seem endless; smart home, healthcare, entertainment, and science are all areas that can benefit from connectivity of low power electronics. But there are obstacles to overcome. Meeting the specifications, especially the phase noise requirements of modern high-speed wireless standards can be a challenge for devices that run on low supply voltages and are allowed only very limited power consumption. The focus of this thesis is the exploration of modern LC-oscillator architectures for RF-transceivers, and the design and post-layout evaluation of a Digitally Controlled Oscillator (DCO) intended to be used in an All-Digital Phase Locked Loop (ADPLL) in a 22 nm FD-SOI process. The DCO specifications are set by an ADPLL for the Wi-Fi 6 (MCS 11) standard. The ADPLL is replacing the blocks that are usually implemented as noise-sensitive analog components with more robust digital blocks that are easier to integrate with baseband- and digital-circuitry. A dual-core class-C oscillator with a dynamic-biasing circuit is proposed and designed to meet the specification of -121 dBc/Hz phase noise at a 1 MHz offset from 7.8 GHz, a –7.18.6 GHz tuning range, and a frequency resolution of at most 35 kHz around 7.8 GHz. The phase noise specification is met; a phase noise of -121 dBc/Hz at the 1 MHz offset from 7.8 GHz is achieved in post-layout simulation along with a Figure of Merit (FoM) of 189.9, and an average tracking frequency step of 5.8 MHz. The tuning range specification was not met, but it is reasonable to believe that the specified range can be met after some redesign of the capacitor banks. Further work will be required.