Sökning: "Gautham Prabhakar"

Hittade 1 uppsats innehållade orden Gautham Prabhakar.

1. 1. Validation of efficiency of formal verification methodology for verification closure

   Master-uppsats, KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Författare :Gautham Prabhakar; [2022]
   Nyckelord :UVM; formal verification; assertions; verification engineers; SVA; TLV; jasper gold; UVM; formell verifiering; assertions; verifierar; SVA; TLV; jasper gold;

   Sammanfattning : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. LÄS MER